The present invention generally relates to differential amplifiers, and in particular to a low power high speed precision comparator.
Comparators are typically employed as an interface between analog signal intelligence and a logic system, or as a circuit means for detecting low level logic signals in the presence of noise. Comparators normally accept two analog input signals and provide an output signal therefrom indicating whether the difference between the input signals is positive or negative. If the output signal is to be at Transistor-Transistor Logic (TTL) levels, there is a fixed high gain requirement from the minimum input voltage to the digital output voltage which normally requires large voltage swings in each amplifier stage. Reduced propagation times are generally desirable but require a high input device slew rate and large overdrive voltages, both of which are obtained at the expense of increased power consumption and heat dissipation. The maximum heat dissipation capacity of integrated circuit packages usually limits the use of comparators in monolithic form. To meet the requirements for comparators in very high speed analog-to-digital (A/D) converters, for example, designers have resorted to complex and costly circuitry, thereby precluding numerous potential applications for comparators.
It is well known that another logic form, Feedback Emitter Coupled Logic (FECL), will operate with smaller voltage swings (130 millivolts versus 2 volts), and hence will operate much faster than TTL. If an integrated circuit used FECL logic levels, at least internally with TTL level output signals, then a dedicated comparator producing lower level (e.g., FECL) output voltages and requiring less power could be incorporated into a monolithic integrated circuit device, such as an A/D converter. However, because of noise problems and temperature sensitivity, FECL compatible devices have not previously been exploited. There is thus a need for a very high speed comparator operating with low voltage swings.